Accelerated Quantum Monte Carlo on a Digital Processor

Accelerated Quantum Monte Carlo with Probabilistic Computers

(a) We use an example problem consisting of a lattice of qubits described by a transverse field Ising model (TFIM). We simulate it classically using the Suzuki-Trotter transformation and calculate a pre-defined order parameter using three different types of hardware whose relative times to solution (TTS) are sketched in (c). The four types of hardware are shown schematically in (b): (1) a von Neumann machine (CPU) – which simulates the problem by breaking down the problem into a series of instructions and executing them sequentially one after another, (2) a physical quantum annealer (QA) that maps the problem onto a network of rf-SQUIDs emulating qubits and rf-couplers coupling those qubits (3) a digital p-computer built using FPGA to lay out a spatial network of interconnected probabilistic p-bits and (4) a clockless p-computer constructed by interconnecting a network of p-bits through resistors.

We demonstrate 2-3 orders of magnitude acceleration of a standard quantum monte carlo algorithm using a specially designed digital processor and a further 2-3 orders of magnitude by mapping it to a clockless analog processor.The clockless analog hardware can be viewed as the classical counterpart of the quantum annealer and provides performance within a factor of of the latter.The time to solution (tts) for the clockless analog hardware scales with the number of qubits as improving the scaling for standard processor implementations, but appears worse than that reported for quantum annealers by d-wave.